The present invention relates to semiconductor integrated circuit memories and, in particular, to memories having built-in self repair (xe2x80x9cBISRxe2x80x9d) circuits.
Semiconductor integrated circuit memories such as static random access memories (xe2x80x9cSRAMsxe2x80x9d) have used BISR circuits to screen for and sometimes repair certain memory failures in the factory and in the field. BISR circuits typically include a state machine, which is fabricated on the integrated circuit with the memory array for implementing a selected test algorithm. This algorithm is initiated in the factory by an external memory tester. In the field, the algorithm is initiated on start-up.
The prevailing method for detecting data retention faults in SRAMs that have BISR circuits is to screen for these faults in the factory. In the factory, the memory and associated BISR circuit are coupled to a memory tester, which provides a supply voltage and a system clock to the memory array and provides control signals to operate the BISR circuit. Typically, memory testers use a two-pass approach through the BISR circuit test algorithm. In the first pass, memory failures are detected and repaired. In the second pass, the repairs are verified.
A common BISR test algorithm consists of several runs through the memory array. The BISR test algorithm performs a sequence of writes and reads on each cell in the memory array, comparing the output of each read with expected data. When a discrepancy is detected, the BISR test algorithm re-maps the memory addresses to replace the row containing the failing cell with a redundant row. These repairs are verified in the second pass through the BISR test algorithm.
During the second pass, the external memory tester also tests the ability of each cell to retain data. After all cells have been written to a definite state by the test algorithm, the external memory tester stops the system clock to halt the test algorithm and lowers the supply voltage provided to the memory array for a sufficient amount of time for weak, leaky or faulty cells to lose their stored charge. The external memory tester then restores the supply voltage and re-starts the system clock to resume the test algorithm. Failing memories are detected by the test algorithm and flagged.
When the memory is installed in the field, the BISR test algorithm is initiated on start-up. It is assumed that all memory failures that were detected and repaired by the BISR circuit in the factory will also be detected and repaired in the field and that all memories with data retention faults were screened out in the factory. However, the inventors of the present invention have found that, in some cases, the first pass through the BISR test algorithm in the factory can mask out certain classes of data retention failures, which prevents them from being detected and repaired in the field. This is due to the fact that, often times, the BISR circuit is clocked at much lower frequencies in the factory than in the field. Since many field systems are now running at extremely high frequencies, the cost or difficulty in making the factory clock match the field clock can be prohibitive.
BISR circuits that are capable of detecting and sometimes repairing certain classes of data retention faults without requiring the factory clock to match the field clock are desired. The present invention addresses these and other problems in the prior art.
One aspect of the present invention relates to a single-chip integrated circuit, which includes a memory array, a built-in self test circuit and a pause circuit. The built-in self test circuit is coupled to the memory array and is adapted to execute a sequence of write and read operations on the memory array. The pause circuit is coupled to and activated by the built-in self test circuit. When activated, the pause circuit pauses the sequence of write and read operations for a pause time period.
Another aspect of the present invention relates to a method of testing an integrated circuit memory array having a plurality of memory locations and an associated built-in self test (BIST) circuit. The BIST circuit implements a memory test algorithm. The method includes setting the BIST circuit to a field mode and initiating the memory test algorithm while the BIST circuit is in the field mode. The memory test algorithm executes a sequence of write and read operations on the memory array in which each of the plurality of memory locations is accessed at least once during first and second runs through the plurality of memory locations. The BIST circuit inserts a pause in the sequence of write and read operations when the BIST circuit is in the field mode such that a maximum time period between subsequent accesses of each of the memory locations is at least as long as the pause.
Another aspect of the present invention relates to a single-chip integrated circuit, which includes a memory array, a built-in self test circuit coupled to the memory array for executing a sequence of write and read operations on the memory array, and a pause circuit coupled to and activated by the built-in self test means for pausing the sequence of read and write operations.